{ "netuid": 84, "slug": "chipforge-tatsu", "name": "ChipForge (Tatsu)", "symbol": "\u30e2", "description": "The World's First Decentralized Chip Design Project", "priceTao": 0.003262057, "priceUsd": 0.8254671307605457, "athUsd": 0.846213019560509, "change24h": -2.4573033892654075, "change7d": 2.026482008841932, "change30d": -13.0013502957289, "change90d": -2.45, "marketCapUsd": 2854253.104740506, "volume24hUsd": 37317.31886917247, "rootProp": 0.17542552855734533, "liquidityUsd": 2709201.1143164034, "alphaStaked": 1816791.258434626, "activeMiners": 2, "activeValidators": 12, "emissionPct": 0.008865755643615114, "emissionPerDayTao": 1.0, "registrationCost": 201.938003214, "pruningRank": 91, "immunityRemaining": 4821, "sentiment": "Neutral", "githubRepo": "https://github.com/TatsuProject/ChipForge_SN84", "subnetUrl": "chipforge.io", "scorecard": { "adoption": { "label": "weak", "score": 9, "reasons": [ { "tone": "neutral", "label": "Stars", "value": "2", "weight": null }, { "tone": "neutral", "label": "Contributors", "value": "3", "weight": null }, { "tone": "neutral", "label": "24h volume", "value": "$37,317", "weight": null }, { "tone": "neutral", "label": "Validators", "value": "12", "weight": null }, { "tone": "negative", "label": "Bus factor", "value": "Top contributor: 90%", "weight": null }, { "tone": "neutral", "label": "LLM blend", "value": "heuristic=3 \u00d7 0.6 + llm=17 \u00d7 0.4", "weight": null } ] }, "shipSpeed": { "label": "weak", "score": 30, "reasons": [ { "tone": "neutral", "label": "Commits 30d", "value": "6", "weight": null }, { "tone": "neutral", "label": "Merged PRs 30d", "value": "0", "weight": null }, { "tone": "neutral", "label": "Releases 12m", "value": "0", "weight": null }, { "tone": "positive", "label": "Latest push", "value": "2026-04-27T11:25:24Z", "weight": null }, { "tone": "positive", "label": "Momentum", "value": "accelerating (6/30d vs 2/mo avg)", "weight": null }, { "tone": "neutral", "label": "LLM blend", "value": "heuristic=37 \u00d7 0.6 + llm=19 \u00d7 0.4", "weight": null } ] }, "updatedAt": "2026-04-29T20:41:08.736068+00:00", "confidence": 0.82, "usefulness": { "label": "watch", "score": 41, "reasons": [ { "tone": "neutral", "label": "Durable keywords", "value": "0 matched", "weight": null }, { "tone": "positive", "label": "Commodity risk", "value": "0 matched", "weight": null }, { "tone": "neutral", "label": "Subnet traction", "value": "1/30", "weight": null }, { "tone": "neutral", "label": "LLM blend", "value": "heuristic=31 \u00d7 0.6 + llm=55 \u00d7 0.4", "weight": null } ] }, "codeQuality": { "label": "weak", "score": 16, "reasons": [ { "tone": "negative", "label": "CI", "value": "Missing", "weight": null }, { "tone": "negative", "label": "Tests", "value": "Missing", "weight": null }, { "tone": "positive", "label": "Docs", "value": "Structured (600 chars)", "weight": null }, { "tone": "negative", "label": "Dep mgmt", "value": "None", "weight": null }, { "tone": "negative", "label": "PR reviews", "value": "0.0 avg, 0% self-merge", "weight": null }, { "tone": "neutral", "label": "Commit quality", "value": "5% conventional", "weight": null }, { "tone": "neutral", "label": "Security hygiene", "value": "No SECURITY.md", "weight": null }, { "tone": "neutral", "label": "LLM blend", "value": "heuristic=14 \u00d7 0.6 + llm=18 \u00d7 0.4", "weight": null } ] } }, "marketScore": 10.0, "githubScore": 22.0, "aiScore": 31.0, "masterScore": 19.0, "masterRating": "F", "lastUpdatedAt": "2026-04-29T20:21:48Z", "isStale": false, "masterScorePrev": 21.0, "purpose": { "title": "ChipForge (Tatsu)", "source": "llm", "confidence": 0.72, "shortSummary": "ChipForge (SN84) proposes decentralized chip design via Verilog/SystemVerilog miner competitions targeting AI accelerators, cryptographic modules, and mini-GPUs. The concept is genuinely novel but the network is effectively non-functional with only 2 active miners and zero merged PRs or releases in the past year. Development velocity is nearly stalled and community traction is minimal." }, "analysis": { "risks": [ "Only 2 active miners \u2014 the network is functionally hollow; a competitive chip design subnet requires many skilled hardware engineers, and current participation signals a severe bootstrapping failure", "Zero merged PRs in 30 days, zero releases in 12 months, and a commit message quality score of 0.05/1.0 indicate near-complete development stagnation, with no CI, no tests, and no lint config present in the repo" ], "score": 31, "summary": "ChipForge (SN84) proposes decentralized chip design via Verilog/SystemVerilog miner competitions targeting AI accelerators, cryptographic modules, and mini-GPUs. The concept is genuinely novel but the network is effectively non-functional with only 2 active miners and zero merged PRs or releases in the past year. Development velocity is nearly stalled and community traction is minimal.", "provider": "cascade:sonnet", "expiresAt": "2026-05-29T20:37:12.589146+00:00", "strengths": [ "Genuinely novel concept \u2014 first decentralized chip design subnet on Bittensor, targeting a real and expensive domain (silicon design) with structured on-chain Verilog/SystemVerilog challenges", "12 active validators providing baseline network stability despite near-zero miner participation", "Has a license and documented README explaining the subnet's challenge model, giving it more foundational structure than many early-stage subnets" ], "updatedAt": "2026-04-29T20:37:12.589146+00:00", "durability": "weak", "recommendation": "Avoid until the miner count grows beyond single digits and at least one public chip design challenge has been completed end-to-end with verifiable outputs; the concept is differentiated but the network has not yet demonstrated it can function.", "dimensionScores": { "adoption": 17, "shipSpeed": 19, "usefulness": 55, "codeQuality": 18 } }, "repoCoverageStatus": "covered", "image": "https://www.chipforge.io/icon.png", "repos": [ { "netuid": 84, "repoKind": "primary", "provider": "github", "owner": "TatsuProject", "name": "ChipForge_SN84", "url": "https://github.com/TatsuProject/ChipForge_SN84", "source": "registry", "isArchived": false, "isFork": false } ], "repoSnapshots": [ { "fullName": "TatsuProject/ChipForge_SN84", "description": "ChipForge (SN84) introduces the first digital design subnet for decentralized hardware innovation. This subnet enables miners to compete in designing real silicon. Processor development is organized into on-chain challenges \u2014 spanning AI accelerators, cryptographic modules, mini-GPUs, and other critical components. ", "homepageUrl": "https://www.chipforge.io/", "defaultBranch": "master", "stars": 2, "forks": 3, "watchers": 0, "contributors": 3, "commits30d": 6, "commits90d": 7, "mergedPrs30d": 0, "mergedPrs90d": 0, "releases12m": 0, "openIssues": 0, "closedIssues30d": 0, "languages": [ { "name": "Python", "percentage": 99.1 }, { "name": "Shell", "percentage": 0.9 } ], "topics": [ "bittensor", "chipforge", "subnet", "tatsu", "sn84", "bittensor-subnet", "hardware-designs" ], "rootSignals": { "hasCi": false, "hasTests": false, "hasLintConfig": false, "hasFormatterConfig": false, "hasTypeScript": false, "hasLicense": true, "hasSecurityPolicy": false, "hasDocs": true, "hasDocker": false, "hasDependabot": false, "hasRenovate": false, "rootEntries": [ ".env.example", ".gitignore", "LICENSE", "MINER_CLI_COMMANDS.md", "README.md", "chipforge", "docs", "neurons", "python_scripts", "requirements.txt", "setup.py", "start_miner.sh", "start_validator.sh", "submit_solution.sh" ] }, "readmeExcerpt": "ChipForge SN84 ChipForge SN84 introduces the first digital design subnet for decentralized hardware innovation. This subnet enables miners to compete in designing real silicon. Processor development is organized into on-chain challenges \u2014 spanning AI accelerators, cryptographic modules, mini-GPUs, and other critical components. Participants download specifications, leverage AI tools, and submit complete Verilog/SystemVerilog implementations. The highest-quality designs earn rewards while contributing to fully manufacturable chips. In the short term, ChipForge focuses on advancing digital hardw", "pushedAt": "2026-04-27T11:25:24Z", "isArchived": false, "isFork": false, "commitMessageQuality": 0.05, "selfMergeRatio": 0.0, "avgReviewsPerPr": 0.0, "hasBranchProtection": false, "topContributorPct": 0.9, "avgCommentsPerIssue": 0.0, "avgResponseHours": 0.0, "prMergeHoursP50": 39.5, "prMergeHoursP95": 39.5, "contributorChurn30d": 0.0, "vulnerabilityCount": 0 } ], "externalLinks": [ { "label": "Website", "href": "https://chipforge.io" }, { "label": "GitHub", "href": "https://github.com/TatsuProject/ChipForge_SN84" } ], "priceHistory": [ { "timestamp": "2025-12-26T20:59:48-03:00", "value": 0.99999159 }, { "timestamp": "2025-12-27T20:59:48-03:00", "value": 0.99161002 }, { "timestamp": "2025-12-28T20:59:48-03:00", "value": 1.01536436 }, { "timestamp": "2025-12-29T20:59:48-03:00", "value": 1.0213093 }, { "timestamp": "2025-12-30T20:59:48.001000-03:00", "value": 1.06086213 }, { "timestamp": "2025-12-31T20:59:48.001000-03:00", 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full RV32F floating-point support for the ChipForge MCU, with significant infrastructure improvements deployed across the platform.\n\nBrief Summary\nBuilding on Challenge 0013's floating-point foundation, we've launched Challenge 0014 to implement the remaining RV32F instructions\u2014including division, square root, fused multiply-add, comparisons, load/store, and full CSR support. This completes the single-precision floating-point extension for our IoT MCU. In parallel, the challenge server received major upgrades to improve transparency, performance tracking, and submission lifecycle management. All services underwent extensive testing to ensure stability and reliability.\n\nChip Design Team\n- Challenge 0014 launched, targeting full RV32F extension completion for ChipForge MCU\n- Miners now implementing: FDIV, FSQRT, fused MAC (FMADD/FMSUB/FNMADD/FNMSUB), comparisons (FEQ/FLT/FLE), FCLASS, FLW/FSW + compressed variants, and full fflags/frm/fcsr CSR support\n- Designs must remain bit-exact with Spike and fully IEEE 754 compliant\n- Extensive testing conducted to ensure challenge stability and correctness\n- Additional robustness measures introduced to maintain evaluation integrity\n\nChallenge Server\n- Added EXHAUSTED status tracking to better manage submission lifecycle through rebatch cycles\n- Introduced `downloaded_at` column and migration tracking for improved submission state visibility\n- Leaderboard enhancements: now exposes per-validator status, evaluation timing, and submission progress counters\n- Split validator performance metrics into passed-design and failed-design average times with separate counts for clearer insights\n- Replaced bulky `evaluation_details` in leaderboard responses with compact preview + dedicated full-logs endpoint for better performance\n- Miner info endpoint now exposes batch window sizes, allowing validators to self-configure internal timeouts dynamically\n- These changes are on testnet.\n\nValidator, EDA Server & Website\n- All services tested extensively and operating smoothly\n- No updates required; systems stable and ready for Challenge 0014 traffic", "created_at": "2026-04-26T18:34:07-03:00", "likes": 26, "retweets": 3, "replies": 3, "views": 739, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2048111378972725724", "handle": "TatsuEcosystem", "text": "Challenge 14 is live! Complete RV32IMCKF Processor\n\nWe're launching the next challenge to complete full RV32F support in our ChipForge IoT MCU.\nBuilding on Challenge 13's floating-point foundation, miners will now implement: FDIV, FSQRT, fused MAC, FEQ/FLT/FLE, FCLASS, FLW/FSW + compressed, and full fflags/frm/fcsr. Bit-exact with Spike. IEEE 754 throughout.\nThe final piece of full RV32F support \u2014 let's forge it. \ud83d\udd25\n\ud83d\udd17 https://t.co/zMZcq7e77I", "created_at": "2026-04-25T15:46:19-03:00", "likes": 36, "retweets": 4, "replies": 0, "views": 964, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2046027929268961548", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 April 19, 2026\nChallenge 0012 has concluded with strong progress, and work has now moved forward on both stabilizing CoralNPU and expanding the ChipForge MCU.\n\nBrief Summary\nChallenge 0012 wrapped up with correctness reaching ~81%, showing solid improvement but still short of a complete fix. During debugging, another issue was identified in the CoralNPU debug interface, where certain instruction patterns report incorrect values despite correct execution. In parallel, Challenge 0013 has been launched on the ChipForge MCU to add floating-point support, and it has already received a fully functional submission from a miner.\n\nChip Design Team\n- Challenge 0012 completed with correctness saturating around ~81%\n- Identified a second issue in CoralNPU related to the debug port, where repeated writes to the same register are not reflected correctly in the debug interface\n- This issue is confirmed and may be taken up as a future challenge\n- Launched Challenge 0013 on ChipForge MCU, focused on adding support for 14 basic floating-point instructions\n- Received a fully correct FPU implementation from a miner early in the challenge\n- Current design runs at ~51 MHz on Sky130, with scope for improvement in frequency and area\n- Challenge will continue for a few more days to push better implementations from miners\n- Next challenge (0014) planned to complete full RISC-V single-precision floating-point extension\n\nChallenge Server, Validator & Website\n- Challenge server updated with a relaunch mechanism that restores previous state and allows challenges to restart cleanly\n- Fixed multiple backend issues including repeated batch execution and challenge status inconsistencies\n- Improved logging system with controlled size and retention, keeping only useful debug information\n- Validator updated with better timeout handling, richer evaluation details, and improved submission reliability\n- Added new fields like evaluation details, timeout flags, and reward eligibility tracking for better transparency\n- Website updated with improved leaderboard visibility, including baseline scores and detailed evaluation breakdown per submission\n- All updates (except website changes) tested on testnet and successfully promoted to mainnet.\n\nChallenge 0012 moved us closer to a stable CoralNPU baseline, and Challenge 0013 has already shown strong early results on the MCU side. Let\u2019s continue pushing for better designs before moving to the next stage.", "created_at": "2026-04-19T21:47:26-03:00", "likes": 29, "retweets": 3, "replies": 0, "views": 600, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2043443241362817134", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 April 12, 2026\nChallenge 0012 is nearing completion, with strong participation from miners and visible progress on fixing the CoralNPU bug.\n\nBrief Summary\nWith only a couple of days remaining in Challenge 0012, miners have actively competed and pushed multiple improved submissions. Some designs have crossed the minimum correctness threshold, reaching scores around ~75%, and are already earning emissions. While this is good progress, the bug is still not fully resolved, and further improvements are needed to push toward full correctness. Depending on the final outcome, the challenge may be relaunched to continue progress. In parallel, the team has found some more bugs in the NPU and significantly improved EDA Server performance.\n\nChallenge 0012 Bug Fixing\n- Challenge 0012 is in its final days, with strong miner participation and multiple submissions across a wide score range\n- Several designs have crossed the minimum threshold (~70%), with top scores reaching ~74.99% and ~75.63%\n- Miners are already earning emissions for improved designs\n- Further work is needed to push correctness closer to 100%\n- Depending on final results, the challenge may be relaunched to continue improving the fix\n\nChip Design Team\n- Identified issues in the CoralNPU debug/verification interface where some instructions appear incorrect on the debug port despite executing correctly\n- The issue is confirmed, and further debugging is ongoing to clearly categorize and understand all related cases before starting a fix\n- Miners also helped surface some issues on the verification side, which were quickly debugged and resolved by the team\n- Upcoming challenges remain planned and will be launched once the current bug-fixing phase is completed\n\nEDA Server\n- Identified and fixed critical storage growth issue that was significantly slowing down design evaluation\n- Evaluation time dramatically reduced after resolving storage bottleneck\n- Removed unused Verilator and OpenLane result files, further improving storage efficiency and cleanup processes\n- Server performance now significantly faster and more stable\n\nWebsite\n- Leaderboard updated to be more miner-friendly, improving visibility of individual scores and comparisons across submissions\n\nLet's finish this challenge strong and push correctness higher so we can move forward with a solid NPU.", "created_at": "2026-04-12T18:36:48-03:00", "likes": 33, "retweets": 5, "replies": 0, "views": 959, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2041025413519220777", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 April 5, 2026\nChallenge 0011 did not lead to a complete fix, so the bug-fixing effort has been relaunched as Challenge 0012, with stronger early participation from miners.\n\nBrief Summary\nAs the bug was not resolved in Challenge 0011, we relaunched the effort as Challenge 0012, where miner participation has already been better in the first few days. While some progress is visible, the bug is still not fully fixed. In parallel, we engaged with the community through an AMA session and discussions, sharing updates and direction. At the same time, upcoming challenges are already planned, but parts of the validation setup still need deeper understanding before they are ready to go live.\n\nCommunity & Updates\n- Held an AMA session with @SubnetSummerTAO, recording available here: https://t.co/2T2z21QkE5\n- Follow-up questions were discussed on Telegram, covering challenges, validation flow, and overall direction\n\nChallenge 0012 Bug Fixing\n- Challenge 0012 is live as a continuation of the unresolved issue from Challenge 0011\n- The bug fix could take some time as the current best submission has reached ~51.65% functionality, but still far from minimal fix (70%), and the full fix (100%)\n- No complete solution yet, further improvement is needed from miners to fully resolve the issue\n\nChip Design Team\n- The validation setup for the upcoming bug-hunting challenge is not finalized yet, some edge cases and issues still need deeper analysis before it can be safely launched\n- The bug-hunting challenge is already planned and will follow once the validation pipeline is stable\n- In parallel, we plan to continue work on the MCU alongside ongoing NPU efforts\n- Preparation of MCU-related challenges has already started, building on the processor developed earlier\n- These will be launched once the current bug is resolved and the bug-fixing phase has had enough time to run\n\nChallenge 0012 is still in progress, and the bug remains unresolved for now. The bug-hunting challenge is planned but depends on stabilizing the validation pipeline first. MCU challenges are also lined up and will follow once the current phase has had enough time to run. The validator, subnet codebase, and website continue to operate smoothly in the background.", "created_at": "2026-04-06T02:29:13-03:00", "likes": 53, "retweets": 10, "replies": 1, "views": 1354, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2040111629103489203", "handle": "TatsuEcosystem", "text": "Had a great time breaking down everything we're building with ChipForge on Subnet 84. From AI accelerators to RISC-V cores \u2014 decentralized chip design is here. Give it a listen if you haven't yet. \ud83c\udfa7", "created_at": "2026-04-03T13:58:10-03:00", "likes": 48, "retweets": 7, "replies": 2, "views": 2939, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2040067705584410841", "handle": "TatsuEcosystem", "text": "RT @SubnetSummerTAO: \ud83d\udd25 Subnet Summer AMA - ChipForge (Subnet 84) \ud83d\udd25\n\nIn this episode, we sit down with the team behind ChipForge, @TatsuEcos\u2026", "created_at": "2026-04-03T11:03:38-03:00", "likes": 34, "retweets": 13, "replies": 1, "views": 6097, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2039445308623474870", "handle": "TatsuEcosystem", "text": "Challenge 0011 is back \u2014 now as CoralNPU RTL Bug Fix.\nDebug and fix bugs in the CoralNPU RISC-V vector processor RTL. The buggy design fails certain vector instruction sequences. Miners must identify and fix the issues to achieve the target functionality score.\nThis is real chip design, not a simulation. Show us what you've got.\nLive now on ChipForge(SN84).\nhttps://t.co/b4sFHXeH36", "created_at": "2026-04-01T17:50:27-03:00", "likes": 54, "retweets": 10, "replies": 4, "views": 1966, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2038351977718161417", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 March 29, 2026\nWith Challenge 0011 wrapped up, the team is shifting focus toward designing the next challenge and investing in smarter infrastructure to support the road ahead.\n\nBrief Summary\nChallenge 0011 has concluded, and while no miner was able to fully resolve the bug, the team is already moving forward. Work is underway on designing the next miner challenge, and R&D has begun on an agent-based validation pipeline to automate and strengthen the verification process. The goal remains the same: build a full loop where miners design, verify, break, and fix.\n\nChip Design Team\n- Challenge 0011 has ended. No miner was able to fully resolve the bug in the CoralNPU, confirming the issue's complexity.\n- Actively designing and preparing the next miner challenge, building on lessons learned from the CoralNPU debugging experience.\n- Began R&D on an agent-based validation pipeline to automate and strengthen the validation process. The goal is to reduce manual validation overhead while increasing robustness and detection capability.\n- The bug hunting challenge remains on the roadmap, with the validation infrastructure work feeding directly into making that challenge viable.\n\nChallenge 0011 Recap\n- The challenge ran its full duration but the bug proved too complex for miners to resolve within the timeframe.\n- Insights from this round are being folded into the design of upcoming challenges.\n\nChallenge 0011 may not have landed a fix, but it reinforced the importance of the path we are on. The next challenge is already being shaped, and with agent-based validation now in R&D, we are actively building the infrastructure to move faster and more reliably going forward. The validator, subnet codebase, and website continue to operate smoothly in the background.", "created_at": "2026-03-29T17:25:56-03:00", "likes": 41, "retweets": 6, "replies": 5, "views": 1198, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2038216622876602726", "handle": "TatsuEcosystem", "text": "Chip design shouldn't be locked behind closed doors. Join us Monday with @SubnetSummerTAO as we break down how SN84 is opening up silicon innovation on @bittensor \u2014 where the best design wins....", "created_at": "2026-03-29T08:28:05-03:00", "likes": 57, "retweets": 9, "replies": 0, "views": 3275, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2038213780388405546", "handle": "TatsuEcosystem", "text": "RT @SubnetSummerTAO: \ud83d\udea8 Subnet Summer AMA - Subnet 84 ChipForge\n\n\ud83d\udd57 8:00 PM AEDT (Monday, 30th March) | 10:00 AM CET (Monday, 30th March)\n\nJo\u2026", "created_at": "2026-03-29T08:16:48-03:00", "likes": 42, "retweets": 10, "replies": 0, "views": 5769, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2037672996450836798", "handle": "TatsuEcosystem", "text": "If you\u2019re wondering how SN84 validates hardware designs from miners and why ChipForge takes time to launch new challenges\u2026\n\nIt\u2019s not about writing the task.\nIt\u2019s about proving we can judge it correctly.\n\nA simple 64-bit adder has 2\u00b9\u00b2\u2078 input combinations (~3.4\u00d710\u00b3\u2078).\nEven with an NVIDIA RTX 5090, brute-force testing would take on the order of 10\u00b9\u2077 years.\n\nAnd modern SoCs are thousands of times more complex than a simple adder.\n\nSo validation isn\u2019t about testing everything.\nIt\u2019s about building a pipeline that can find real issues early and reliably.\n\nWe have already found and fixed bugs in Google\u2019s Coral NPU.\nThis shows that our validation pipeline is capable of handling real, complex hardware designs at an industrial level.\n\nBuilding such a validation pipeline takes time.\n\nFull breakdown \ud83d\udc47\ud83d\udc47", "created_at": "2026-03-27T20:27:55-03:00", "likes": 51, "retweets": 8, "replies": 1, "views": 1341, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2037669450095440347", "handle": "TatsuEcosystem", "text": "https://t.co/jquCfRoP0x", "created_at": "2026-03-27T20:13:49-03:00", "likes": 35, "retweets": 3, "replies": 0, "views": 1745, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2035820359526785428", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 March 22, 2026\nImagine miners not only designing the frontend RTL of a chip, but contributing across the entire chip design flow, from design to verification, and eventually even physical design. That is the direction we are moving toward.\n\nBrief Summary\nWith Challenge 0011 now live, miners are already helping fix real issues in the CoralNPU. This marks the start of the verification phase, where the focus shifts from building the core to strengthening it. Alongside this, we are working on finalizing the bug hunting challenge, where miners will be working together to break the chip. This way miners will be working on designing the RTL, breaking the chip, and then fixing it as well. Covering the full spectrum of frontend design, and later on we will extend this flow toward backend development to include physical design as well.\n\nChip Design Team\n- Challenge 0011 is live, where miners are actively contributing in fixing a bug in the CoralNPU.\n- This builds on earlier work where miners helped design the processor core, and now extends into the verification and bug-fixing phase.\n- Preparing the next challenge focused on bug hunting, where miners will actively try to break the design.\n- For the bug hunting challenge, we are working on making the validation pipeline robust enough to safely handle arbitrary miner-submitted test programs.\n- Exploring ways to involve miners not just in testing the chip, but also in strengthening the verification environment itself.\n- In parallel, the team has outlined the next steps for the ChipForge MCU, with upcoming challenges planned to continue from where we left off in November 2025.\n\nChallenge 0011 Bug Fixing\n- Challenge 0011 is currently focused on fixing known issues in the CoralNPU.\n- The issue is more involved than expected and may take some time to be fully resolved.\n- Early progress is visible, a miner has already improved the functionality score from 30 to 40, showing clear improvement in the design with partial fix.\n\nThis week was more about planning than execution. The direction is clear, build a full loop around the chip, where miners design, verify, break, and fix. This approach will help speed up the overall chip design cycle while reducing both development time and cost.\nThe validator, subnet codebase, and website continue to operate smoothly in the background.", "created_at": "2026-03-22T17:46:12-03:00", "likes": 47, "retweets": 6, "replies": 1, "views": 1216, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2034880134092554624", "handle": "TatsuEcosystem", "text": "RT @opentensor: The largest decentralised LLM pre-training run in history.\n\nSN3 @tplr_ai trained Covenant-72B across 70+ contributors on op\u2026", "created_at": "2026-03-20T03:30:04-03:00", "likes": 1688, "retweets": 363, "replies": 77, "views": 119111, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2033476343481163885", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 March 15, 2026\nThe work from the previous weeks has now reached an important milestone. Challenge 0011 has been prepared and launched, focusing on fixing real issues discovered in CoralNPU while continuing to strengthen the verification pipeline around it.\n\nBrief Summary\nChallenge 0011 is now live, shifting the focus from only finding bugs to also fixing them. In parallel, we made the ChipForge MCU repository public, sharing the processor core that was developed step by step through decentralized hardware challenges on this subnet. With the MCU core now open, the team has started preparing the next set of challenges aimed at expanding it into a complete microcontroller platform.\n\nChip Design Team\n- Challenge 0011 finalized and launched, allowing participants to work on fixing real issues identified in CoralNPU.\n- Continued monitoring and validation of the bug-fix pipeline to ensure solutions submitted by participants are evaluated correctly.\n- Published the ChipForge MCU repository, making the processor core developed through challenges on this subnet publicly available.\n- The core is a 32-bit RISC-V processor with hardware cryptography acceleration, implemented in SystemVerilog and extensively verified against the Spike ISA simulator across millions of executed instructions.\n- The repository includes RTL, verification infrastructure, and documentation so the development process and validation approach are fully transparent.\n- Work has begun on preparing the next challenges focused on expanding this processor core toward a complete MCU platform.\n\nChallenge 0011 Bug Hunting\n- Challenge 0011 is now live and focused on fixing real issues discovered in CoralNPU.\n- The validation pipeline is actively evaluating submitted fixes using the improved verification infrastructure.\n- Continued monitoring to ensure fair and consistent validation of miner submissions.\n\nThe direction remains clear. Stabilize the core designs first, then build on top of them. Bug discovery and bug fixing together will help ensure both CoralNPU and the ChipForge MCU become strong foundations for the next generation of challenges on this subnet.", "created_at": "2026-03-16T06:31:55-03:00", "likes": 46, "retweets": 8, "replies": 4, "views": 1464, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2032553681619706001", "handle": "TatsuEcosystem", "text": "Debug and Fix the Coral NPU Vector Processor\n\nChallenge 0011 is Now Live on ChipForge!\nWe are launching our first challenge on Google's Coral NPU, a RISC-V vector processor where certain illegal vector instructions trigger incorrect RTL behavior. Your task is to identify and fix the bug.\n\nChallenge Overview\nThe CoralNPU (RV32 + V extension) currently fails when some illegal vector instruction sequences are executed. \nFix the bug in the Chisel source, regenerate the SystemVerilog RTL, and improve the functionality score.\n\nTarget Score: \u226570%\nDuration: 2 weeks\n\nGetting Started (For Miners)\n1. Clone the repo: https://t.co/mBuFCJVOUR \n2. Checkout commit `16711f3` \n3. Fix the bug in Chisel source \n4. Generate `https://t.co/lrlG67zg8s` \n5. Test using the miner evaluator and submit if your score \u226570%\n\nSubmission\nSubmit a `.zip` with generated SystemVerilog RTL: \nhttps://t.co/RaiEyc1U0p\n\u251c\u2500\u2500 rtl.f\n\u2514\u2500\u2500 https://t.co/lrlG67zg8s \n\nResources\nCoral NPU: https://t.co/mBuFCJVOUR \nLeaderboard: https://t.co/b4sFHXfeSE \n\nGood luck miners! Let\u2019s fix this bug in the Coral NPU together.", "created_at": "2026-03-13T17:25:35-03:00", "likes": 37, "retweets": 5, "replies": 1, "views": 1320, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2031555780756029802", "handle": "TatsuEcosystem", "text": "We\u2019ve made the ChipForge MCU (MicroController Unit) repository public.\n\nThis processor core was developed through decentralized hardware competitions on ChipForge, Bittensor SN84, where miners submit RTL designs and our validation system evaluates them across functionality, performance, area, and power.\n\nOver multiple challenges, the design evolved step by step. Different implementations were tested, optimized, and verified through our automated validation pipeline.\n\nWhat is available today is the processor core itself \u2014 a 32-bit RISC-V architecture with hardware cryptography acceleration, implemented in SystemVerilog and verified extensively against the Spike ISA simulator across millions of executed instructions.\n\nThis repository contains the RTL, verification infrastructure, and documentation so anyone can see exactly what has been built and how it was validated.\n\nThis is the first big achievement of ChipForge, and the starting point for what comes next.\n\nThe upcoming challenges will expand this processor core into a complete MCU (MicroContoller Unit) platform by adding further ISA extensions, enabling RTOS support, integrating debug through JTAG and GDB, and introducing system peripherals to turn the processor into a full microcontroller SoC.\n\nIn parallel, work is continuing toward the ChipForge NPU (Neural Processing Unit). That path is naturally more complex and will take longer due to the challenges of matrix engines, compiler support, and deeper hardware-software co-design.\n\nHuge credit to the miners who contributed designs and pushed this effort forward.\n\nhttps://t.co/Pd7zltJD83", "created_at": "2026-03-10T23:20:17-03:00", "likes": 53, "retweets": 5, "replies": 2, "views": 1530, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2030729459624743388", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 March 8, 2026\nWork from the previous week carried forward as the team continued investigating the CoralNPU behavior discovered during the PR71 effort, while pushing the Challenge 0011 validation pipeline closer to a stable launch state.\n\nBrief Summary\nThe CoralNPU issue discovered during the PR71 work turned out to be more involved than initially expected, and the team is still working toward the correct fix. In parallel, we continued strengthening the Challenge 0011 validation pipeline. Since miners will submit many different kinds of test programs, the system must handle any possible input fairly. The team has been generating a wide range of internal test cases to stress the pipeline before launch. Alongside bug hunting, we are also considering a bug fixing challenge based on issues already identified in CoralNPU.\n\nChip Design Team\n- Continued investigation of the CoralNPU issue discovered during the PR71 work. The bug is still not fully resolved and the team is actively working toward the correct fix.\n- Ongoing debugging around vector pipeline behavior to understand the remaining corner cases before finalizing the patch.\n- Continued improvements to the Challenge 0011 evaluator pipeline to make validation more reliable.\n- Generated additional internal test programs to stress the validation pipeline and ensure it can handle different miner submissions.\n\nChallenge 0011\n- Validation pipeline continues to be tested against many different types of test inputs.\n- Corner cases are being addressed to ensure miner submissions are validated fairly and consistently.\n- The earlier challenge may initially focus on fixing known CoralNPU bugs that have already been identified and reproduced.\n- Bug hunting will then come as next challenge, allowing miners to submit programs that expose new issues.\n\nBug hunting, and then the ability to fix those bugs, can help ensure the baseline CoralNPU is stable before moving onward to increasing its ability to support further extensions, gain better performance, while still staying at very low power.", "created_at": "2026-03-08T16:36:46-03:00", "likes": 34, "retweets": 4, "replies": 2, "views": 1126, "is_retweet": false, "is_reply": false, "media_type": null }, { "tweet_id": "2028208079813382628", "handle": "TatsuEcosystem", "text": "Sunday Brief \u2013 March 1, 2026\nAnother focused verification week for TATSU. Continued stress testing uncovered deeper issues, while infrastructure was refined for cleaner, faster evaluation.\n\nBrief Summary\nThis week strengthened correctness. A regression after our upstream trap fix revealed a vector recovery gap, and further stress testing confirmed a serious arithmetic flaw in the shared multiply/divide path. In parallel, we streamlined the Challenge 0011 evaluator, removing false positives, improving determinism, and accelerating simulation. The system is sharper and more reliable than last week.\n\nChip Design Team\n- Identified a post-trap vector stall caused by incomplete recovery signaling, some fixes already applied but the bug is still not fully fixed yet.\n- Confirmed a critical vector division edge-case that corrupts the shared multiply/divide unit. This bug is also closely related to the PR71 illegal instruction issue.\n- Added major changes in the Challenge 0011 evaluator, simplified execution model, reduced simulation time so that validators take less time to validate the submitted bug by the miners.\n- Updated the EDA server to use a diff spike version that works in our verification environment.\n\nChallenge 0011 Bug Hunting\n- Evaluator pipeline validated end-to-end.\n- Stable Spike vs Coral comparison achieved.\n- Preparing for subnet integration.\n\nChallenge Server\n- Infrastructure updates underway to fully support the revised evaluation pipeline.\n- Latest testing confirms stable operation across all active services.\n\nSubnet Codebase\n- Final adjustments in progress to enable full validator support for Challenge 0011.\n- Ongoing compatibility checks ahead of activation.", "created_at": "2026-03-01T17:37:43-03:00", "likes": 39, "retweets": 5, "replies": 1, "views": 1139, "is_retweet": false, "is_reply": false, "media_type": null } ] }